Modern integrated circuits (ICs) are developed through the use of hardware description languages (HDLs). HDLs such as VERILOG, VHDL, and the like allow developers to create software-based representations of circuit designs. One advantage of using an HDL is the potential for code reuse from one design to another. This concept has been realized with the commercial availability of intellectual property (IP) cores.
In general, an IP core (hereinafter “core” or “module”) refers to a software representation of a semiconductor component that provides a processing function. Different varieties of cores exist. For example, some cores can provide basic functions that can be included in a circuit design or, alternatively, can be used as subcomponents within a larger, more complex core. Another variety of cores can function as a logic bridge to software-based bus objects, such as Peripheral Component Interconnect (PCI) or Advanced Microcontroller Bus Architecture (AMBA) busses.
Some cores are highly configurable and prior to release undergo extensive testing to verify whether or not the core is functionally correct. A common approach to verification of a core is with a testbench. A testbench, also referred to as a verification environment, provides test stimuli and verifies the behavior of a design under test, in this case one or more cores. Generating a testbench involves describing the connections, events, and test vectors for different combinations of transactions involving the one or more cores. A testbench also refers to the code used to create a pre-determined input sequence to the cores, as well as the code responsible for observing the response.
However, the order of events within an event time in an event file associated with testing a core may be non-deterministic. This non-deterministic behavior can cause the generated test vectors to be incorrectly applied, thus causing false negatives in testing the core.
Accordingly, systems for and methods of enabling a simulation of a circuit design using a testbench that account for the timing of events are desirable.